1. Field of the Invention
The present invention relates to a semiconductor memory device and a layout method for a semiconductor memory device. More specifically, the present invention provides a semiconductor memory device and a layout method for arranging a semiconductor memory device without increasing chip size while increasing memory capacity.
2. Description of the Related Art
In a conventional layout method for arranging signal lines of memory cell arrays in a semiconductor memory device, word lines and I/O lines are disposed in the same direction with each other. Column select signal lines and bit lines are disposed in a row direction as intersecting the word lines. This general signal line layout method can integrate many memory cells.
However, in recent years, it has become necessary for a semiconductor memory device to include a number of data I/O lines that is more than the number of column select signal lines, in order to increase the number of bits transferred per second, in accordance with the development of graphic fields. Accordingly, a layout method for arranging signal lines different from the conventional layout method is used in the graphic fields. That is, in the layout method of the graphic fields, word lines and column select signal lines are disposed in the same direction with each other, and bit lines and I/O lines are disposed as intersecting the word lines.
FIG. 1 is a block diagram illustrating one type of a conventional semiconductor memory device. The device includes memory cell array blocks 10-1, 10-2, . . . , and 10-8, row decoders 12-1, 12-2, . . . , and 12-8, column decoders 14-1, 14-2, . . . , and 14-9, and column predecoder 16. Column select signal lines CSL0, CSL1, CSL2 and CSL3 are disposed in a row direction. I/O line pairs(IO1, IO1B), (IO2, IO2B), . . . , and (IOm, IOmB) are disposed in a column direction as intersecting the column select signal lines CSL0, CSL1, CSL2 and CSL3. The column select signal lines are commonly connected to two adjacent memory cell array blocks. For example, the column select signal lines CSL2 and CSL3 between the memory cell array blocks 10-1 and 10-2 select the memory cell array block 10-1 when the memory cell array block 10-1 is activated, or select the memory cell array block 10-2 when the memory cell array block 10-2 is activated.
Eight row decoders 12-1, 12-2, . . . , and 12-8 input and decode row address RA0-k of k bits, the row decoders 12 becoming active in response to block select signals BLS0, BLS1, . . . , and BLS7.
The column predecoder 16 generates decoding output signals CA0B1B, CA01B, CA0B1, and CA01 by decoding column address CA0 and CA1. Responding to the block select signal BLS0 at a high level, the column decoder 14-1 activates the column select signal line CSL0 when the decoding output signal CA0B1B is at a high level and activates the column select signal line CSL1 when the decoding output signal CA01B is at a high level. Responding to the block select signal BLS7 at a high level, the column decoder 14-9 activates the column select signal line CSL0 when the decoding output signal CA0B1B is at a high level or activates the column select signal line CSL1 when the decoding output signal CA01B is at a high level. Responding to the block select signal BLS0 or BLS1 at a high level, the column decoder 14-2 activates the column select signal line CSL2 when the decoding output signal CA0B1 is at a high level or activates the column select signal line CSL3 when the decoding output signal CA01 is at a high level. The column decoders 14-3, . . . , and 14-8 activate the column select signal lines CSL0, CSL1, CSL2 and CSL3 with the same method as the column decoder 14-1 or 14-2.
FIG. 2 is a circuit diagram illustrating one configuration of the column predecoder 16 of FIG. 1. The column predecoder 16 includes inverters I1, I2, I3, I4, I5 and I6, and NAND gates NA1, NA2, NA3 and NA4. The inverters I1 and I2 invert the column address CA0 and CA1, respectively. The circuit including NAND gate NA1 and inverter I3 generates the decoding output signal CA0B1B at a high level when inputting output signals of the inverters I1 and I2 at a high level. The circuit including NAND gate NA2 and inverter I4 generates the decoding output signal CA01B at a high level when inputting output signals of the column address CA0 and inverter I2 at a high level. The circuit including NAND gate NA3 and inverter I5 generates the decoding output signal CA0B1 at a high level when inputting an output signal of the inverter I1 and the column address CA1 at a high level. The circuit including NAND gate NA4 and inverter I6 generate the decoding output signal CA01 by inputting the column addresses CA0 and CA1 at a high level.
FIG. 3 is a circuit diagram illustrating one configuration of one of the column decoders 14 of FIG. 1. The column decoders 14 each include a NOR gate NOR1, inverters I7, I8 and I9, and NAND gates NA5 and NA6. In FIG. 3, signals C1 and C2 denote two block control signals applied to each of the column decoders 14-1, 14-2, . . . , and 14-9 of FIG. 1. Signals I1 and I2 denote two decoding output signals (CA0B1B, CA01B) and (CAOB1, CA01), respectively, applied to each of the column decoders 14-1, 14-2, and 14-9 of FIG. 1. Signals O1 and O2 denote two column select signals output from each of the column decoders 14-1, 14-2, . . . , and 14-9 of FIG. 1.
Operation of the circuit illustrated in FIG. 3 will now be described. The circuit including NOR gate NOR1 and inverter I7 generates an output signal at a high level in the case in which at least one signal of signals C1 and C2 is at a high level. The circuit including NAND gate NA5 and inverter I8 outputs the input signal I1 as the output signal O1 by responding to an output signal of the inverter I7 at a high level. The circuit including NAND gate NA6 and inverter I9 outputs the input signal I2 as the output signal O2 by responding to an output signal of the inverter I7 at a high level.
FIG. 4 is a detailed block diagram illustrating one configuration of the memory cell array block 10-2 of FIG. 1. The memory cell array block includes memory cells 20-11, 20-12, . . . , 20-1(4m), 20-21, 20-22, 20-2(4m), . . . , 20-n1, 20-n2, . . . , and 20-n(4m), precharge circuits 22-1, 22-2, . . . , and 22-(4m), sense amplifiers 24-1, 24-2, . . . , and 24-(4m), and I/O gates IOG1, IOG2, and IOG(4m).
Word lines WL1, WL2, . . . , and WLn of the memory cell array block 10-2 are disposed in the same direction as the column select signal lines CSL0, CSL1, CSL2 and CSL3. Bit line pairs (BL1, BL1B), (BL2, BL2B), . . . , and (BL(4m), BL(4m)B) are disposed in the same direction as I/O line pairs (IO1, IO1B), . . . , and (IOm, IomB).
Also, the memory cells 20-11, 20-12, . . . , 20-1(4m), 20-21, 20-22, . . . , 20-2(4m), . . . , 20-n1, 20-n2, . . . , and 20-n(4m) are connected between the word lines WL1, WL2, . . . , and WLn and bit line pairs (BL1, BL1B), (BL2, BL2B), . . . , and (BL(4m), BL(4m)B), respectively. The I/O gate IOG1, I/O gates IOG5(not shown), . . . , and IOG(4m-3) are connected to the column select signal line CSL0. The I/O gate IOG3, I/O gates IOG7(not shown), . . . , and I/O gate IOG(4m-1) are connected to the column select signal line CSL1. The I/O gate IOG4, I/O gates IOG8(not shown), . . . , and I/O gate IOG(4m) are connected to the column select line CSL2. The I/O gate IOG2, I/O gates IOG6(not shown), . . . , and IOG(4m-2) are connected to the column select signal line CSL3.
Data I/O operation of the circuit illustrated in FIG. 4 will now be described. In the case of writing data into the memory cells 20-12, 20-14, . . . , and 20-1(4m), when the write command is applied to the device, the precharge circuits 22-1, 22-2, . . . , and 22-(4m) operate to precharge the bit line pairs (BL1, BL1B), (BL2, BL2B), . . . , and (BL(4m), BL(4m)B), respectively. The word line WL1 is enabled and the column select signal line CSL2 is selected and the I/O gate IOG4, I/O gates IOG8(not shown), . . . , and the I/O gate IOG(4m) are turned on. Data transferred through data I/O line pairs (IO1, IO1B), . . . , and (IOm, IomB) are transferred to the sense amplifiers 24-4, . . . , and 24-(4m), respectively. The sense amplifiers 24-4, . . . , and 24-(4m) amplify and transfer the data to the corresponding bit line pairs (BL4, BL4B), . . . , and (BL(4m), BL(4m)B). The data transferred to the memory cells 20-14, . . . , and 20-1(4m) is written.
In the case of reading data from the memory cells 20-14, . . . , and 20-1(4m), when the read command is applied to the device, the precharge circuits 22-1, 22-2, . . . , and 22-(4m) operate to precharge the bit line pairs (BL1, BL1B), (BL2, BL2B), . . . , and (BL(4m), BL(4m)B), respectively. The word line WL1 is enabled and the column select signal line CSL2 is selected and the I/O gate IOG4, the I/O gates IOG8, (not shown), and the I/O gate IOG(4m) are turned on. The data stored in the memory cells 20-14, . . . , and 20-1(4m) is transferred to the corresponding bit line pairs (BL4, BL4B), . . . , and (BL(4m), BL(4m)B). The sense amplifiers 24-4, . . . , and 24-(2m) amplify the data transferred to the bit line pairs (BL4, BL4B), . . . , and (BL(4m), BL(4m)B) and then transfer the data to the data I/O line pairs (IO1, IO1B), . . . , and (IOm, IOmB).
The conventional semiconductor memory device as illustrated in FIG. 1 requires a large chip size due to the large number of column select signal lines, if the memory cell array block becomes larger in the row direction. If the size of the memory cell array blocks 10-1, 10-2, 10-3, and 10-4 illustrated in FIG. 1 are enlarged two times in a row direction and the number of the column select signal lines CSL0, CSL1, CSL2 and CSL3 is increased two times, a semiconductor memory device is constructed as illustrated in FIG. 5 according to a conventional layout method.
FIG. 5 a block diagram illustrating another configuration of a conventional semiconductor memory device. The device of FIG. 5 includes memory cell array blocks 30-1, 30-2, 30-3 and 30-4, row decoders 32-1, 32-2, 32-3 and 32-4, column decoders 34-1, 34-2, 34-3, 34-4 and 34-5, and column predecoders 36 and 38.
In FIG. 5, the size of the memory cell array blocks 30-1, 30-2, 30-3 and 30-4 is two times larger than that of FIG. 1, and the number of the column select signal lines CSL0, CSL1, . . . , and CSL7 is increased two times more than that of FIG. 1. The memory cell array blocks are enlarged by two times in a row direction, so that the number of the column select signal lines is increased by two times.
FIG. 6 is a circuit diagram illustrating one configuration of the column predecoder 36, 38 of FIG. 5, comprising inverters I10, I11, I12, I13 and I14. The three inverters I10, I11 and I12 connected in series generate a decoding output signal CA2B by buffering and inverting a column address CA2. The two inverters I13 and I14 connected in series generate a decoding output signal CA2 by buffering and inverting the column address CA2.
FIG. 7 is a circuit diagram illustrating one configuration of the column decoder 34 of FIG. 5. Each column decoder 34 includes a NOR gate NOR2, NAND gates NA10, NA11, NA12 and NA13 and inverters I15, I16, I17, I18 and I19.
Referring to FIG. 7, control signals C1 and C2 denote two block select signals applied to each of the column decoders 34-1, 34-2, . . . , and 34-5. Input signals I1, I2, I3 and I4 denote four decoding output signals CAOB1B, CAO1B, CAOB1 and CAB1 output from the column predecoder 36. An input signal I5 denotes one of two decoding output signals CA2B and CA2 output from the column predecoder 36.
Operation of the circuit illustrated in FIG. 7 will now be described. The circuit including a NOR gate NOR2 and inverter I15 generates a signal at a high level when one control signal of two control signals C1 and C2 is at a high level by ORing the control signals C1 and C2. The circuit including a NAND gate NA10 and inverter I16 outputs the input signal I1 as an output signal O1 by responding to an output signal of the inverter I15 at a high level and the input signal I5. The circuit including a NAND gate NA11 and inverter I17 outputs the input signal I2 as an output signal O2 by responding to the output signal of the inverter I15 at a high level and the input signal I5. The circuit including a NAND gate NA12 and inverter I18, and the circuit including a NAND gate NA13 and inverter I19 output the input signals I3 and I4 as output signals O3 and O4, respectively, by responding to the output signal of the inverter I15 at a high level and the input signal I5, respectively.
FIG. 8 is a detailed block diagram illustrating the cell array block 30-2 of FIG. 5. 8m memory cells MC are connected to word lines WL1, WL2,, and WLn. Four column select signal lines CSL0, CSL1, CSL2 and CSL3 are disposed at the lower portion of the memory cell array block 30-2. The remaining four column select signal lines CSL4, CSL5, CSL6 and CSL7 are disposed at the upper portion of the memory cell array block 30-2. And the eight column select signal lines CSL0, CSL1, . . . , and CSL7 are connected to I/O gates IOG1, IOG2, . . . , and IOG8, respectively.
FIG. 8 illustrates the connection among the memory cells, I/O gates and column select signal lines of memory cell array block 30-2 shown in FIG. 5, showing that the number of the I/O gates and column select signal lines is increased as two times since the capacity of the memory cells is enlarged as two times in a row direction. That is, in case of arranging the semiconductor memory device by the conventional layout method, the capacity of the memory array blocks is enlarged as two times in a row direction, and then the number of the I/O gates and column select signal lines is increased as two times. Accordingly, chip size is enlarged. Also, the line loading of the column select lines is increased since the column select lines become longer according to the increasing capacity of the memory cell array blocks.